When both registers are loaded (decimal number 65536), the first next pulse causes an overflow, reset occurs and counting starts from zero. Each coming pulse increments the number stored in the 16-bit register by 1. ![]() Timer 2 is enabled by setting the TR2 bit of the TCON register.First, it is necessary to write a number from which the counting starts to a 16-bit register (TH2+TL2).This is so called Capture mode in which the value of the counter register (consisting of RCAP2H and RCAP2L) can be “captured” and copied to the capture register (consisting of RCAP2H and RCAP2L), thus not affecting the counting process. If the CP/RL2 bit of the T2CON register is set, timer 2 operates according to the figure below. 0 - Under the same condition, signal on the T2EX pin will cause a number to be transferred from capture to counter register.1 - If EXEN=1, pulse on the T2EX pin will cause a number to be transferred from counter to capture register.0 - 16-bit register (T2H and T2L) counts pulses from the oscillator (timer).ĬP/RL2 is timer 2 capture/reload bit used to define transfer direction:.1 - 16-bit register (T2H and T2L) counts pulses on the C/T2 pin (counter).TR2 is timer 2 run control bit used to enable/disable timer 2:Ĭ/T2 is timer/counter 2 select bit used to select pulses to be counted by counter/timer 2: 1 - Signal on the T2EX pin affects timer 2 operation.0 - T1 is used as transmit clock for serial port.ĮXEN2 is timer 2 external enable bit used to include the T2EX pin in timer 2 operation:.1 - T2 is used as transmit clock for serial port.TCLK is transmit clock bit which determines which timer is to be used as transmit clock for serial port: 0 - T1 is used as receive clock for serial port.1 - T2 is used as receive clock for serial port.RCLK is receive clock bit which determines which timer is to be used as receive clock for serial port: The EXF2 bit must be cleared from within the program. ![]() It generates an interrupt (if enabled), unless the DCEN bit of the T2CON register is set. If bits RCLK and TCLK are set, overflow has no effect on the TF2 bit.ĮXF2 bit is automatically set when a capture or a reload is caused by a negative transition on the T2EX pin. In order to detect the next overflow, this bit must be cleared from within the program. TF2 bit is automatically set on timer 2 overflow. This register contains bits controlling the operation of timer 2. Similar to T0 and T1, it has four different modes of operation to be described later in this chapter. ![]() The main adventage of this timer compared to timers 0 and 1 is that all read and swap operations are easily performed using one instruction. They are used to temporarily store the contents of the counter register. Another two registers, RCAP2H and RCAP2L, are also serially connected and operate as capture registers. Like timers 0 and 1, it can operate either as a timer or as an event counter. Two of them, TH2 and TL2, are connected serially in order to form a larger 16-bit timer register. Unlike timers T0 and T1, this timer consists of 4 registers. Timer 2 is a 16-bit timer/counter installed only in new versions of the 8051 family. ![]() Timers T0 and T1 completely fall under the 8051 Standard. The AT89S8253 has three timers/counters marked as T0, T1 and T2.
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